In the field of integrated circuits, the need is felt for providing integrated circuits having a preset time constant depending on the product RC of a capacitance value C by a resistance value R.
For example, in the state of the art, it is known to provide integrated circuits of which the cut-off frequency is a linear (particularly, inversely proportional) function of the product RC of a resistance R by a capacitance C. The process for producing these integrated circuits has inherent variations such that the product RC obtained can sensibly differ from the desired product RC. In some cases, the variations can be as high as 40% or 50% in module and this entails that there may also be a factor of 3 between the lowest and highest cut-off frequencies of the filter achievable by the manufacturing process.
This gives rise to a problem, for example with a low-pass filter, in that:                when the effective cut-off frequency of the filter is higher than the desired value, the filter can let undesired noise pass therethrough, mainly when the latter is present about the desired cut-off frequency;        on the contrary, when the effective cut-off frequency of the filter is lower than the desired value, the useful signal is dampened.        
To solve these problems, several solutions have been developed in the art, which provide carrying out, after the integration process, the so-called trimming of the wafers on which the circuits are made. However, these solutions suffer from high costs in terms of additional area occupied, in terms of time required for testing the circuits, and further offer poor reliability. Furthermore, in some cases, these solutions are not feasible, mainly because the productive technology applied not always provides for the components required for implementing these solutions.
An alternative solution to that of the above-mentioned prior art has been published in “IEEE JOURNAL OF SOLID-STATE CIRCUITS”, vol 38, No. 5, May 2003, in the article “A Highly Integrated Analog Front-End for 3G”, and provides a self-adjusting circuit that, as compared with the trimming solutions described above, has lower consumptions and lower area costs.
The self-adjusting circuit of the above-cited article is schematically represented in FIG. 1, in which it is generally designated with 1. In the article, the self-adjusting circuit 1, or calibration circuit 1, is used for adjusting the time constant RC of a low-pass filter 2, and is such to provide a calibration signal to this filter via the bus REG_BUS. The low-pass filter 2 is such as to receive an input signal to be filtered I_sig to output a corresponding filtered signal F_sig.
The calibration circuit 1 includes a calibration loop comprising a switched capacitor array C_AR, an analog comparator CMP, a control and timing logic unit TG_CNT and an interruption element SW_Res controllable by a signal Res_C and suitable to reset the switched capacitor array C_AR by short-circuiting the latter to ground.
The array switched capacitors C_AR can be selectively switched via a signal provided by the control and timing unit TG_CNT to a bus C_BUS. The switched capacitor array C_AR is shown in FIG. 2a in greater detail.
In FIG. 2a, the array C_AR comprises four capacitors 8C, 4C, 2C, 1C, or modular capacitive elements, which are binary weighted relative to a unit capacitance of value C. The precision of the calibration circuit can be either increased or decreased by providing a higher or lower number of modular capacitive elements, respectively.
The symbols B3,B2, . . . , B0 indicate the bits of the control signal supplied to the array C_AR via the C_BUS, from the most significant bit to the least significant bit, respectively. By Sw3, . . . , Sw0 have been designated the capacitor switches, 8C, . . . , 1C, controlled by the respective bits B3, . . . , B0. These switches allow selectively connecting/disconnecting (i.e., enabling/disabling) the capacitors of the array C_AR to/from node 4, the voltage of the latter being designated with VRC in FIG. 1. It should be observed that the effective capacitance Ceff in the capacitor array C_AR depends, in a given instant, on which and how many modular capacitive elements 8C, 4C, 2C, 1C are connected to the node 4 via the switches Sw3, . . . , Sw0. It should be also observed that the capacitor array C_AR comprises a fixed capacitor Cfx, which is the lowest capacitance value required for obtaining the calibration in the case where the product RC of the filter 2 such as obtained by the process has a highest value relative to the tolerance range normally ensured by the process. The total capacitance value which can be set in parallel with the fixed capacitor Cfx via the modular capacitive elements 8C, 4C, 2C, 1C must be established, on the contrary, such as to be capable of ensuring the granularity required by the calibration.
The calibration cycle carried out by the circuit in FIG. 1 is intended to identify by trial and error a control code B3, B2, B1, B0 (produced by the timing and control logic unit TG_CNT and provided thereby to the array C_AR via the bus C_BUS) which is such as to identify a set of array enabled capacitors C_AR such as to meet a preset calibration condition. At the end of the calibration cycle, the control code B3,B2,B1,B0 obtained is sent via the bus REG_BUS to the filter 2 and represents the calibration signal. In the filter 2, this code is applied to the adjustable capacitance Cvar in order to obtain a preset RC=R*Cvar product in the filter 2.
Waveforms illustrating the operation of the circuit in FIG. 1 are reported in FIG. 2b. 
With reference to FIG. 1, 2a, 2b, the timing and control logic unit TG_CNT is such as to start a calibration cycle in response to a calibration-request signal C_REG and according to a timing imposed by a clock signal CK. At the beginning of each step of the calibration cycle, the timing and control logic unit TG_CNT is such as to short-circuit the array C_AR to ground, by closing the interruption element SW_Res, in order to discharge this array C_AR.
After the array has been discharged C_AR, the interruption element SW_Res is opened for a half-period of the clock signal and a certain number of modular capacitive elements 8C, . . . , 1C are connected to the node 4, by a selective closure of the switches Sw3, . . . , Sw0 that is commanded by the control code B3, . . . , B0.
These modular capacitive elements 8C, . . . , 1C start charging thus causing the voltage VRC of node 4 to increase according to a transient characterized by a time constant equal to RF*Ceff and an asymptote given by the voltage Vcc. As stated above, Ceff represents the effective capacitance value (including the fixed capacitance value Cfx) of the array C_AR which are connected to node 4 at a given instant.
In a clock half-period, when the voltage VRC of node 4 reaches a voltage higher than voltage VCMP=VCC*R2/(R1+R2), the analog comparator CMP will change its output state (in the example, the signal OUT_CMP will go from logic level “0” to logic level “1”).
The clock signal CK is a clock having a known frequency and there exists only one product RF*Ceff being such as to cause the voltage VRC to increase to the value VCMP in a half-period of clock signal CK. For this reason, the VCMP is set at a voltage value equal to the voltage that node VRC would achieve in a clock half-period according to a transient governed by a time constant 1/RC equal to, except for a scale factor, the desired value at which the time constant of filter 2 has to be calibrated.
In the particular circuit described in the above-cited article, the control codes sent from the timing logic unit TG_CNT to the array C_AR are generated by a counter of this unit, which is decremented at each step of the calibration cycle. This counter has a number of resolution bits equal to the number of the modular capacitive elements 8C, 4C, 2C, 1C that can be controlled by means of the control signal.
With particular reference to FIG. 2b, it should be observed that upon operation, before starting a calibration cycle, the signal RES_C short-circuits the capacitors Cfx, 8C, 4C, 2C, 1C of the array C_AR to earth until when the calibration cycle is started and the switches Sw3, . . . , Sw0 on the capacitors are such as to turn them off when they are driven with 0 or turn them on when they are driven with 1.
The switches Sw3, . . . , Sw0 are driven via the bits B3, . . . , B0 of the control code provided on the bus C_BUS. This code B3, . . . , B0 corresponds to the value of the unit counter TG_CNT. The counter, during the calibration cycle, is decremented from the initial value 15 (in the case of 4 bits) by a unit at each period of clock signal CK.
At each decrement of the counter there corresponds a decrease, within the array C_AR, by one capacitive unit.
The first attempt (or first step) of the calibration circuit is carried out with all the capacitors of the array C_AR being enabled. When the level reached by the voltage VRC in a half-period of the clock signal CK is lower than the value of the voltage VCMP, the counter will be decremented by one unit. Consequently, also the subsequent control code B3, . . . , B0 will decrease by one unit, and thus the total capacitance of the array C_AR will be decreased by one elementary capacitor. This occurs, however, only after the array C_AR has been previously short-circuited to earth by the interruption element SW_Res in the half-period subsequent to the attempt described above.
During the subsequent steps, the calibration cycle is carried out by unit decrements in the subsequent steps until when the voltage value VRC achieved in one half-period is higher than the voltage VCMP. In the latter case, the cycle ends and the value reached in the counter is stored, which value will be then used as the code to be applied to the filter for calibration and sent to the latter via the bus REG_BUS.
The prior art solution described above suffers from several drawbacks. Particularly, it requires a low-offset and fast comparator CMP, to avoid excessively penalizing the calibration precision, especially when the clock signal CK to be used is a high-frequency signal. This implies area occupation and additional power consumption and design difficulties.